Peripheral component interconnect express (PCIe) communication links include short serial communication links, which may be used to connect peripheral devices to a computer or to connect servers, for example. PCIe communication links generally conform to a PCIe standard, which establishes a standard layout for a PCIe standard bus and correspondingly a PCIe connector that may be included in peripheral devices. The PCIe standard is used throughout the computer industry and provides interchangeability of peripheral devices as well as establishes design criteria used in the development of peripheral devices.
Specifically, the PCIe standard designates certain channels in a PCIe standard bus for communication of payload data and other channels in the PCIe standard bus for communication of status data. The payload data may include general data used in applications and the status data may include data rate negotiation, the presence or readiness of a peripheral device, and the like.
According to the PCIe standard, the data (payload data and/or status data) may be communicated on payload data channels, which may be configured into groups of four lanes or multiples of four lanes. The lanes are generally constructed using copper components. However, the copper components limit signaling speeds and limit distances over which the data may be communicated. Moreover, recent developments in the PCIe standard seek to increase the payload data speeds and users are seeking longer distances for physically larger systems.
The subject matter claimed herein is not limited to embodiments that solve any disadvantages or that operate only in environments such as those described above. Rather, this background is only provided to illustrate one example technology area where some embodiments described herein may be practiced.